Semiconductor memory devices typically include a large number of memory cells, each of which can store one or more bits of data. The memory cells are arranged in an array, having a number of rows and columns. Memory cells within the same row are commonly coupled to a word line, and memory cells within the same column are commonly coupled to a bit line. The memory cells within an array are accessed according to the various memory device operations. Such operations include read operations (common to nearly all memory devices), write operations (common to volatile memory devices), and program and erase operations (common to many nonvolatile memory devices). To access memory cells, an external memory address is applied, which activates a word line. When activated, row decoder circuits couple the data stored within the memory cells to the bit lines of the array. The memory address also activates column decoder circuits, which connect a given group of bit lines to input/output circuits and/or program/erase circuits.
In the course of fabricating a semiconductor memory device, manufacturing defects can give rise to nonfunctional memory cells within an array. In order to preserve the functionality of devices having defective memory cells, redundant memory cells are often used. Redundant memory cells are extra memory cells that are used to replace defective memory cells. A typical redundancy scheme includes row-wise redundancy, in which one or more extra rows of memory cells are created within the array. In the event an applied memory address corresponds to a row having a defective memory cell, one of the extra rows of memory cells is accessed in lieu of the row containing the defective memory cell. Redundancy schemes utilizing column-wise redundancy are also well known.
Referring now to FIG. 1, a dynamic random access memory (DRAM) is set forth in a block schematic diagram, and designated by the general reference character 100. The DRAM 100 includes a timing control circuit 102, an address buffer 104, a row decoder 106 and a column decoder 108. The timing control circuit 102 receives externally applied control signals (CTRLX) and generates therefrom internal controls signals (CTRLI) which are applied to the address buffer 104 and to a memory array 110. The address buffer 104 receives externally applied address signals (ADDX) and generates decode signals (DEC). In response to the DEC signals, the row decoder 106 and the column decoder 108 select a memory cell, or group of memory cells within the memory array 110. An input/output (I/O) circuit 112 allows data to be written to, or read from, the column decoder 108.
A portion of the memory array 110 is illustrated in more detail in FIG. 2. The memory array 110 includes a matrix of memory cells 202 coupled to bit lines and word lines. Bit lines 204 are shown extending from the top of the memory cell matrix 202 to a bit line equalization circuit 206, and from the bottom of the memory cell matrix 202 to a transfer gate circuit 208. Word lines are not shown in FIG. 2. The transfer gate circuit 208 is disposed between the bit lines 204 and a bank of sense amplifiers 210. Among the internal control signals (CTRLI) received by the memory array 110, are a bit line equalization signal EQ, a transfer gate enable signal TG, and a sense amplifier enable signal SA. The EQ signal, when high, equalizes bit line pairs by shorting the bit lines together. The TG signal, when high, enables the transfer gate circuit 208, coupling the bit lines 204 to the bank of sense amplifiers 210. The SA signal, when high, enables the bank of sense amplifiers 2l0, which amplifies data signals on the bit lines 204.
One type of read operation for the memory array portion 110 is set forth generally, in the timing diagram in FIG. 3. Referring now to FIG. 2 in conjunction with FIG. 3, at the start of a read operation, an externally applied row address strobe signal (/RAS) goes low. The falling edge of the /RAS signal drives a word line (WL) within the memory cell matrix 202 high, coupling a row of memory cells to the bit lines 204 of the memory cell matrix 202. Data signals are present on the bit lines. The TG signal goes high in response to the rising edge of the WL signal, and the bit lines are coupled to the bank of sense amplifiers 210. The SA signal is driven high in response to the rising edge of the TG signal, and the bank of sense amplifiers 210 is enabled, amplifying the voltages on the bit lines. At the end of the read cycle, the EQ signal goes high, equalizing the bit lines 204.
Having described the general structure and operation for one type of memory device, one conventional way of implementing a redundancy scheme will now be described. Referring now to FIG. 4, a DRAM array is designated by the general reference character 400, and is shown to include a bit line equalization circuit 402 and a transfer gate circuit 404, disposed at opposite ends of a memory cell matrix 406. The memory cell matrix 406 includes standard memory cells 408 and redundant memory cells 410. The standard memory cells 408 are coupled to bit lines BL0-BL5 and word lines WL0-WL3. The standard memory cells 408 are designated by the reference character Mi,j, where i represents the memory cell word line, and j represents the memory cell bit line. The redundant memory cells 410 are coupled to redundant word lines RWL0 and RWL1, and to the same bit lines as the standard memory cells 408 (BL0-BL5).
The bit line equalization circuit 402 is shown to include a shorting transistor Q0-Q2, each having a source-drain path coupled between pairs of bit lines (BL0/BL1, BL2/3, and BL4/5). The gates of the shorting transistors (Q0-Q2) commonly receive the EQ signal. The transfer gate circuit 404 is shown to include pairs of transfer gate transistors, Q3/Q4, Q5/Q6 and Q7/Q8, each of which couples a pair of bit lines to a sense amplifier (SA0-SA2) within a bank of sense amplifiers 4l2.
The redundancy scheme illustrated in FIG. 4 illustrates a conventional row-wise redundancy case. A row having a defective memory cell can be replaced by a row of redundant memory cells. For example, in the event a standard memory cell is defective, the entire row containing the defective memory cell can be replaced by a row of redundant memory cells. For example, if the memory cell M10 was defective, memory cells M10, M12 and M14 could be replaced by RM10, RM12 and RM14. The substitution of redundant rows for "bad" standard rows is accomplished by driving redundant word line RWL0 in response to an address that corresponds to word line WL11. The conventional row-wise redundancy described in FIG. 4 is advantageous because defects in other rows, memory cell M21, for example, can be replaced by the second redundant row (i.e., memory cells M21 and M22 replaced by RM01 and RM02). Thus, assuming all the redundant memory cells are functional, in a worst case situation, at least two memory cells can be replaced.
While the conventional memory cell array architecture set forth in FIG. 4 is conducive to the row-wise redundancy scheme described, it is not always desirable to construct semiconductor memory devices with such an array architecture. The need for faster, more compact, devices has given rise to unconventional memory device architectures. Such unconventional architectures are not conducive to conventional prior art redundancy approaches.